ATMEGA328PB-AU/TQFP-32

8-bit AVR microcontroller chip

Product details

Introduction

        The picoPower® ATmega328PB is a low-power CMOS 8-bit microcontroller based on the AvR® enhanced RISC architecture. By  executing powerful instructions in a single clock cycle,  the ATmega328PB achieves throughputs close to 1 MlPS per MHz. This empowers system designers to optimize the device for  power consumption versus processing speed.

Features

High Performance, Low-Power AVR® 8-bit Microcontroller Family

Advanced RISC Architecture

      131 Powerful instructions

       Most Single Clock Cyde Execution

       32 x 8 General Purpose Working Registers

       Fully Static Operation

       Up to 20 MIPS Throughput at 20 MHz

       On-Chip 2-Cycle Multiplier

High Endurance Nonvolatile Memory Segments

       32 KB of in-System Self-Programmable Flash program memory

       1 KB EEPROM

       2 KB Intemal SRAM

       Write/Erase Cycles: 10,000 flash, 100,000 EEPROM

       Optional Boot Code Section with independent Lock Bits

             In-System Programming by On-chip Boot Program

             True Read-While-Write Operation

       Programming Lock for Software Security

Peripheral Features

       Peripheral Touch Controller (PTC)

              Capacitive Touch Buttons, Sliders, and Wheels

             24 Self-Cap Channels and 144 Mutual Cap Channels

       Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

       Three 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode

       Real-Time Counter with Separate Oscillator

       Ten PWM Channels

       8-channel 10-bit ADC

       Two Programmable Seral USARTs

       Two Master/Slave SPl Serial Interfaces

       Two Byte-Oriented Two-Wire Serial interfaces

       Programmable Watchdog Timer with Separate On-chip Oscillator

       On-Chip Analog Comparator

       Interrupt and Wake-Up on Pin Change

Special Microcontroller Features

        Power-On Reset and Programmable Brown-Out Detection

        Intemal 8 MHz Calibrated Oscillator

        External and Internal Interrupt Sources

       Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby

       Clock Failure Detection Mechanism and Switch to intemal 8 MHz RC Oscillator in case of Failure

       Individual Serial Number to Represent a Unique lD

I/O and Packages

       27 Programmable l/O Lines

       32-pin TQFP and 32-pin QFN /MLF

Operating Voltage:1.8-5.5V

lemperature Range:-40°C to 105°C

Speed Grade.

       0-4 MHz @ 1.8-5.5V

       0-10 MHz @ 2.7-5.5V

       0-20 MHz @ 4.5-5.5V

Power Consumption at 1 MHz, 1.8V, 25°C

       Active Mode: 0.24mA

       Power-Down Mode: 0.2 μA

       Power-Save Mode: 1.3 μA (induding 32 kHz RTC)

Product Description

         The core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly  connected to the Arithmetic Logic Unit (ALU),  allowing two independent registers to be accessed in a single instruction executed in one clock cyde. The resulting  architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC  microcontrollers.

         The ATmega328PB provides the following features:  32 KB of in-System Programmable Flash with Read While-Write capabilities, 1 KB EEPROM, 2 KB SRAM,  27 general purpose l/O lines, 32 general purpose working registers, five flexible Timer/Counters with compare modes,  internal and external interrupts, two serial programmable USART, two byte-oriented two-wire Seral interface ,  two SPl serial ports, an 8 channel 10-bit ADC in TQFP and QFN/MLF package,  a programmable Watchdog Timer with internal Oscillator. Clock failure detection mechanism,  and six software selectable power saving modes. The ldle mode stops the CPU while allowing the SRAM, Timer/Counters,  USART, two-wire Serial interface, SPI port,  and interrupt system to continue functioning. PTC with enabling up to 24 self-cap and 144 mutual-cap sensors. The  Power-Down mode saves the register contents but freezes the Oscillator,  disabling all other chip functions until the next interrupt or hardware reset. In Power-Save mode,  the asynchronous timer continues to run,  allowing the user to maintain a timer base while the rest of the device is sleeping Also ability to run PTC in  Power-Save mode/wake-up on touch and Dynamic ON/OFF of PTC analog and digital portion. The ADC Noise Reduction mode  stops the CPU and all I/O modules except asynchronous timer, PTC,  and ADC to minimize switching noise during ADC conversions. In Standby mode,  the crystal/ resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up  combined with low power consumption.

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