Original CH482X QFN-20 2 Differential Channel Two-Choice And Four-Pole Double-Throw High-Speed Analog Switch Chip
Original CH482X QFN-20 2 Differential Channel Two-Choice And Four-Pole Double-Throw High-Speed Analog Switch Chip
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CH482X/QFN-20
2 Differential channel two-choice, four-pole double-throw ultra-high-speed analog switch chip
Product Description
CH482D, CH483M, CH483X, CH484M, CH481D and CH486F are differential high-speed signal bidirectional analog switch chips based on RF technology, featuring high bandwidth and low on-resistance.
The CH482D contains a two-channel differential ultra-high-speed signal two-way analog switch, totaling QPDT, which can be used for two-way differential signal two-way switching such as USB 3.0 Super Speed PCle Gen1/2, SATA AVSAS 1.5G/3G/6G, Display Port, etc.
The CH482X function is similar to that of the CH482D but has a higher bandwidth. It can be used for two differential signals such as USB 3.1Gen 2, namely Super Speed+, PCle Gen1/2/3, SATA/SAS 3G/6G, Display Port, etc.
The CH484M contains two differential ultra-high-speed signal four-select analog switches, totaling QPQT, which can be used for four-select and all-switch of two differential signals such as USB 3.0 Super Speed.PCle Gen1/2, SATA/SAS 1.5G/3G, Display Port, etc.
The CH481D features a 2-channel differential ultra-high-speed signal matrix switching analog switch, ExchangeSwitch, which can be used for USB 3.0 Super Speed, pcie Gen1/2, SATA/SAS 1.5G/3G/6G. Direct or cross transmission of two differential signals such as Display Port. For more matrix switching switches or crossover switches for medium and low frequency signals, please refer to the CH449 chip manual.
The CH486F contains two differential high-speed signal four-select analog switches, totaling QPQT, which can be used for four-select and all-switch of two differential signals such as US8 2.0 High Speed, SATA/SAS 1.5G, etc. The DPOT eight-choice switch (8:1 MUX) can refer to the CH448 chip.
The CH483M and CH483X, in addition to incorporating all the modules of the CH482D (referred to as the SS ultra-speed channel), also include one differential high-speed signal two-choice analog switch (referred to as the HS high-speed channel), totaling QPDT+DPDT It can be used for two-way switching of three differential signals such as USB 3.0 Super Speed & USB 2.0 High Speed, PCle Gen1/2 & Refclk, Display Port, etc.
Product features
High bandwidth, SS ultra-speed channel supports 6Gbps differential signal, and supports ultra-speed USB signal.
The CH482X ultra-speed channel supports 10Gbps differential signals and USB3.2 Gen2 signals.
The HS high-speed channel supports 1.5G(4:1) or 2.5Gbps(2:1) differential signals and full-amplitude voltage analog signals.
The HS high-speed channel supports video signals and supports low-speed, full-speed and high-speed USB signals.
The on-resistance is low, with a typical Ron value of approximately 49Ω.
Low crosstalk, high isolation.
It provides a global enable pin, enabling and switching multi-channel analog switches uniformly.
The ESD of the SS overspeed channel supports 2KV HBM, while the ESD of other channels and control pins supports 4KV HBM.
Supports a rated power supply voltage of 3.3V and has low static power consumption.
We offer package forms such as QFN20-2.5X4.5, QFN42-3.5X9 and QFN28, which are compatible with RoHS.
Pin description
| Pin number | Pin name | Type | Pin description |
| 9,20 | VDD | Power supply | Positive power supply, rated 3.3V, requires an external decoupling capacitor |
| 4, 10, 19, 0 | GND | Power supply | Public ground, digital signal reference ground |
| 5 | VDD | Power supply | CH482D: Optional positive power supply, rated at 3.3V |
| NC. | Empty foot | CH482X: No electrical signal connection. It is recommended to connect GND or VDD | |
| 1 |
EN# | Digital input | Global enable input, low level effective: high level disconnected and powered off |
| 8 | SEL |
Digital input |
The selection input of the two-choice analog switch: Select the 1# terminal (SS'1') at a high level, Select the 0# terminal (SS'0') at a low level |
|
2, 3, 6, 7 |
SSAX,SSAY, SSBX, SSBY |
Analog signal | Choose one of the two to simulate the common terminal of the switch |
| 18, 17, 16, 15 |
SSAOX, SSAOY, SSBOX, SSBOY |
Analog signal | At the 0# terminal of the analog switch, the SEL pin input is selected at a low level |
| 14, 13, 12, 11 |
SSA1X, SSA1Y, SSB1X, SSB1Y |
Analog signal | At the 1# end of the analog switch, the SEL pin input high level is selected |
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